Source: CNet

The companies, allies in developing semiconductor manufacturing technology, will present two papers at a chip conference this week outlining how they have reduced power consumption on chips made on the 65-nanometer process.

AMD and IBM have essentially added two technologies to their manufacturing repertoire that strain the silicon layers inside their chips. Straining makes the silicon layers more uniform and rigid, which allows electrons to travel faster. This in turn lets engineers design chips that perform better than existing models, or perform at a similar level but consume less electricity.

One technique, called embedded silicon germanium, involves carving a trench around P-channel transistors and filling in the resulting hole with silicon germanium. The other, called stress memorization, is applied to N-channel transistors. P-channel and N-channel transistors are the two types of transistors: P-channel transistors carry positive charges, or holes, and N-channel carry negatively charged electrons. In straining P-channel transistors, engineers want to increase the density of the atoms, and in N-channel devices to do the opposite.

The companies already added a straining technology called dual-stress liners and silicon on insulator. Opteron processors, as well as Cell chips, will include all of these straining techniques.

Although it does not support silicon on insulator, Intel already incorporates germanium into its chips, as well as technologies similar to dual-stress liners. Which company is ahead, and whose technology is better, remains an ongoing debate between Intel and AMD-IBM.

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The combined straining technologies inserted into the AMD-IBM processes reduce power consumption by 40 percent compared to hypothetical chips that don't include the technology. Chips that didn't include these technologies, though, would be difficult to sell because of the power they would consume.

AMD tried in the past to incorporate strained silicon into its chips through a relationship with AmberWave. AMD encountered manufacturing issues and subsequently killed the alliance.

The new silicon germanium technology uses far less germanium than the earlier technique and is more easily to manufacture, said Nick Kepler, vice president of technology development at AMD.

"Silicon germanium is inherently more difficult to introduce into the process," he said.

AMD will start to come out with chips on the 65-nanometer process in the second half of 2006. Intel and Texas Instruments started churning out 65-nanometer chips at the end of this year.

The papers will come out at the International Electron Devices Meeting, one of the major annual chip design conferences, taking place in Washington, D.C.

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